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[ASAHI KASEI]
[AK7740ET]
AK7740ET
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
1. General Description The AK7740 is a highly integrated audio processing IC, including four 24-bit output D/A channels, a stereo 24-bit input A/D, and an audio DSP. High quality analog output performance is provided by the quad DAC with 97dB dynamic range, and the stereo ADC with 98dB dynamic range. The converters support sampling frequencies from 32kHz to 48kHz. This device includes 72kbits of SRAM audio delay that is suitable for simulated sound fields. The DSP is optimized for audio signal processing. The design allows up to 512 execution lines per audio sample cycle, with multiple functions per line. The AK7740 is ideal for sound field control applications, including echo, 3D, parametric equalization, and speaker compensation. It is housed in a 48-lead LQFP package. 2. Features DSP: Word length: 24-bit (Data RAM) Instruction cycle time: 40ns (512fs, fs=48kHz ) Multiplier: 24 x 16 40-bit Divider: 24 / 24 16-bit or 24-bit ALU: 34-bit arithmetic operation (overflow margin: 4-bits) 24-bit arithmetic and logic operation Shift+Register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left 1, 2, 3, 4, 8 , 14 and 15 bits shifted right Other numbers in parentheses are restricted. Provided with indirect shift function Program RAM: 512 x 32-bit Coefficient RAM: 512 x 16-bit Data RAM: 256 x 24-bit Offset RAM: 48 x 13-bit - (6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit ) - Internal Memory: 72kbit SRAM - Sampling frequency: 32kHz to 48kHz - Serial interface port for micro-controller - Master clock: 512fs - Master/Slave operation - Serial signal input port ( 2 to 4 ch ): 16/20/24-bit : Output port ( 2 ch ): 24-bit ADC: 2 channels - 24-bit 64x over-sampling delta sigma - DR, S/N : 98dBA ( full-differential Input ) - S/(N+D) : 89dB - Digital HPF (fc = 1Hz) - Single-ended or full-differential Input DAC: 4 channels - 24-bit 128x over-sampling advanced multi-bit - DR, S/N : 97dBA - S/(N+D) : 89dB - Single ended or differential output Input Selector - 1 full-differential and 4 single-ended Input Other - Power supply: +3.3V10% - Operating temperature range: -10C~70C - Package: 48pin LQFP (0.5mm pitch) -

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3. Block diagram
LRCLK BITCLK CLKOUT XTI XTO SMODE
OUTAE SDOUTA
LRCLK
BITCLK
CLKOUT
XTI XTO
SMODE
INIT_RESET S_RESET
INIT_RESET S_RESET AINL-
CONTROLLER ADC
AINLAINL+ SW0 SDINA SDIN
SDINA SDIN
SW3
RQ SI SO SCLK RDY DRDY JX
RQ SI SO SCLK RDY DRDY JX
DSP
SDATA
AINL+ AINL1 AINL2 AINL3 AINL4 AINRAINR+ AINR1 AINR2 AINR3 AINR4 VREFH VCOM AOUTL AOUTR AOUTL1 AOUTR1 AOUTL2 AOUTR2
AINRAINR+
ISEL[2:0] SW2 SDOUTD1 SDATA VREF
DAC1
SW2 SDOUTD2 SDOUT SW1 SDOUT SDATA
DAC2
AOUTL AOUTR
72kbit DLRAM
* SW1,SW2,SW3,ISEL[2:0], OUTAE control register
Note)
A B
C
Q
When C is "L"(0) then A connects with Q.
This block diagram is a simplified illustration of the AK7740; it is not a circuit diagram.

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[ASAHI KASEI] AK7740 DSP Block diagram
[AK7740ET]
CP0,CP1 CRAM 512 X 16
DP0,DP1 DRAM 256 X 24
DLP0,DLP1 DLRAM 6K X 12 or 3K X 24 4K X 12 & 1K X 24 CMP(Compress & Expand) OFRAM 48 X 13
CBUS(16bit) DBUS(24bit)
MPX16
MPX24
Micom I/F Control
Serial I/F
X
Y Multiply 16 X 24 -> 40 40bit MUL 24bit DBUS SHIFT 34bit A B
DEC
PRAM 512 X 32 PC Stack : 1level TMP 8 X 24bit PTMP 24bit X 6(LIFO) 2 X 24 bit 2 X 24/20/16bit ADC SDIN
34bit
ALU1 34bit Overflow Margin: 4bit DR0 3 24bit Over Flow Data Generator
Divider 24 / 24 24
2 X 24bit 2 X 24bit
DAC1 DAC2
2 X 24bit
SDOUT

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4. Description of Input/Output Pins (1) Pin layout
48
47
46
45
44
43
42
41
40
39
38
AINL3 AINR2 AINL2 AINR1 AINL1 VREFH AVDD AVSS DVSS DVDD XTI XTO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48pin LQFP (TOP VIEW)
37
AOUTR1
AOUTL1
VCOM
AINR+
AINR3
AINR4
AVDD
AINL+
AINL4
AVSS
AINR-
AINL-
36 35 34 33 32 31 30 29 28 27 26 25
AOUTL2 AOUTR2 BVSS DVSS DVDD INIT_RESET S_RESET RQ SCLK SI SO RDY
SDOUTA
SMODE
BITCLK
SDOUT
LRCLK
SDINA
DRDY
CLKO
Note) JX,SDIN and SDINA are Pull-down pins

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DVSS
SDIN
JX
DVDD
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(2) Pin function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name AINL3 AINR2 AINL2 AINR1 AINL1 VREFH I/O I I I I I I I O O I I Function ADC single-ended analog Lch input pin 3 ADC single-ended analog Rch input pin 2 ADC single-ended analog Lch input pin 2 ADC single-ended analog Rch input pin 1 ADC single-ended analog Lch input pin 1 Analog reference voltage input Connect to AVDD (pin 7), and bypass with 0.1uF and 10uF capacitors between this pin and AVSS. Analog power supply 3.3V typical Analog ground Digital ground Digital power supply 3.3V typical Master clock input Connect a crystal oscillator between this pin and the XTO pin, or input an external CMOS clock signal to the XTI pin. Crystal oscillator output When a crystal oscillator is used, connect between XTI and XTO. When an external clock is used, keep this pin open Clock output Outputs the XTI clock. Allows the output to be set to "L" by control register setting. External condition jump (pulldown) Slave/master mode selector Sets LRCLK and BITCLK to input or output mode. SMODE="L": Slave mode (clock input mode) SMODE="H": Master mode (clock output mode) LR channel select clock SMODE="L": Slave mode: Inputs the fs clock SMODE="H": Master mode: Outputs the fs clock Serial bit clock SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks SMODE="H": Master mode: Outputs 64 fs clocks DSP serial data input ( Pulldown) Compatible with MSB/LSB justified 24, 20 and 16 bits. Classification Analog section
AVDD AVSS DVSS DVDD XTI
Analog Power Supply Digital Power Supply System clock
XTO
System clock Condition input Control
CLKO JX SMODE
System clock
16 17 18 19
LRCLK
I/O I/O I
BITCLK
SDIN
Digital section Serial input data
SDINA
DSP serial data input (Pulldown) I When using the ADC, leave open or connect to DVSS. Compatible with MSB justified 24 bits.

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Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin name SDOUTA
SDOUT DRDY DVSS DVDD RDY SO SI
I/O Function O DSP serial data output Outputs MSB justified 24-bit data selected from ADC or SDOUTD1 by control register setting O DSP serial data output Outputs MSB justified 24-bit data O Output data ready pin for microcontroller interface O O Digital ground Digital power supply 3.3V typical Data write ready output for microcontroller interface Serial data output for microcontroller interfaces Microcontroller interface serial data input and serial data I output control When SI does not use, leave SI="L" Microcontroller interface serial data clock I When SCLK is not used, leave SCLK="H" Microcontroller interface writes request pin. I RQ ="L": Microcontroller interface enable I System Reset I Reset (for initialization) Input "L" to initialize the AK7740 at power-on - Digital power supply 3.3V typical - Digital ground - Substrate ground O DAC2 Rch analog output O DAC2 Lch analog output O DAC1 Rch analog output O DAC1 Lch analog output - Analog power supply 3.3V typical O Common voltage Connect to 0.1uF and 10uF capacitors between this pin and AVSS. Do not connect to external circuitry - An alog ground I ADC Rch analog inverted input I ADC Rch analog non-inverted input I ADC Lch analog inverted input I ADC Lch analog non-inverted input I ADC single-ended analog Rch input 4 I ADC single-ended analog Lch input 4 I ADC single-ended analog Rch input 3
Classification Digital section Serial output data
Microcontroller interface Power supply Microcontroller interface
SCLK RQ S_RESET INIT_RESET DVDD DVSS BVSS AOUTR2 AOUTL2 AOUTR1 AOUTL1 AVDD VCOM
Reset
Power supply Power supply Analog section
Power supply Analog section Power supply Analog section
AVSS AINRAINR+ AINLAINL+ AINR4 AINL4 AINR3

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5. Absolute Maximum Rating (AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground) Item Symbol min max Power supply voltage Analog (AVDD) VA -0.3 4.6 Digital (DVDD) VD -0.3 4.6 |AVSS (BVSS)-DVSS| Note 1) 0.3 GND Input current (except for power supply pin ) IIN 10 Analog input voltage AINL+,AINL-,AINR+,AINR-,AINL1, VINA -0.3 VA+0.3 AINR1,AINL2,AINR2,AINL3,AINR3, AINL4,AINR4,VREFH Digital input voltage VIND -0.3 VD+0.3 Operating ambient temperature Ta -10 70 Storage temperature Tstg -65 150
Unit V V V mA V V C C
Note 1) AVSS(BVSS) should be at the same level as DVSS WARNING: Operation at or beyond these limits may result in permanent damage of the device. Normal operation is not guaranteed when these limits are exceeded 6. Recommended Operating Conditions (AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.) Items Symbol min typ max Unit Power supply voltage AVDD VA 3.0 3.3 3.6 V DVDD VD 3.0 3.3 VA V Reference voltage (VREF) VREFH Note 1) Note 1)
VRH
VA
V
VREFH normally connects to AVDD.
Note: The analog input voltage and output voltage are proportional to VREFH voltage.

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7. Electric Characteristics (1) Analog characteristics (Unless otherwise specified, Ta = 25C; AVDD, DVDD = 3.3V; VREFH = AVDD; BITCLK = 64 fs; Signal frequency 1kHz; Measurement bandwidth = 20Hz to 20kHz @ 48kHz; DSP section in reset state; ADC with all differential inputs) Parameter Min Typ Max Unit Resolution 24 Bits ADC Section Dynamic characteristics S/(N+D) fs = 48kHz (-1dB) (Note1) 80 89 dB Dynamic range fs = 48kHz (A filter) (Note2) 90 98 dB S/N fs = 48kHz (A filter) 90 98 dB Inter-channel isolation (f =1kHz) (Note3) 90 110 dB DC accuracy Inter-channel gain mismatching 0.1 0.3 dB Analog input Input voltage (Differencial) (Note4) Vp-p 1.85 2.00 2.15 Input Voltage (Single-ended) (Note5) 1.85 2.00 2.15 Vp-p Input impedance (Note6) 15 33 k Resolution 24 Bits DAC Section Dynamic characteristics S/(N+D) fs = 48kHz (0dB) 80 89 dB Dynamic range fs = 48kHz (A filter) (Note2) 90 97 dB S/N fs = 48kHz (A filter) 90 97 dB Inter-channel isolation (f =1kHz) (Note7) 90 105 dB DC accuracy Inter-channel gain mismatching (Note7) 0.2 0.5 dB Analog output Output voltage (Note8) 1.85 2.00 2.15 Vp-p Load resistance 10 k Note: 1. Specification only guaranteed for differential inputs 2. Indicates S/(N+D) when -60dB signal is applied 3. Specified for L and R of each input selector 4. Applies to AINL+, AINL-, AINR+ and AINRFullscale (AIN = (AIN+) - (AIN-)) can be represented by (FS = (VREFH-AVSS)x(2.0/3.3)) 5. Applies to AINL1,AINR1,AINL2,AINR2,AINL3,AINR3,AINL4 and AINR4 Fullscale single-ended input is (FS=(VREFH-AVSS) x (2.0/3.3)) 6. Applies to AINL1, AINR1, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4, AINL+, AINL-, AINR+ and AINR7. Specified for L and R of each DAC. 8. Fullscale output voltage when VREFH=AVDD

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(2) DC characteristics (VDD=AVDD=DVDD=3.0~3.6V,Ta=25C) Parameter High level input voltage Low level input voltage High level output voltage Iout=-100A Low level output voltage Iout=100A Input leak current Note 1) Input leak current (pull-down) Note 2) Input leak current (XTI pin) Note: 1. 2. 3. Pins with pull-down resistors and the XTI pin are not included Pull-down pins are JX, SDIN and SDINA. The pull-down resistor value is 156k For input/output levels in this datasheet: the low level will be represented as "L" or 0, and the high level as "H" or 1. In principle, "0" and "1" will be used to represent the bus (serial/parallel) such as registers. Symbol VIH VIL VOH VOL Iin Iid Iix Min 80%VDD VDD-0.5 0.5 10 Typ Max 20%VDD Unit V V V V A A A
22 24
(3) Current consumption (AVDD=DVDD=3.0V~3.6V, Ta=25C; master clock (XTI)=24.576MHz=512fs[fs=48kHz]; When operating 4 DAC channels with a 1kHz sine wave full-scale input to each of ADC analog input pin) Power supply Parameter Power supply current 1) During operation a) AVDD b) DVDD c) Total (a+b) 2) INIT_RESET ="L" Power consumption 1)During operation a) AVDD b) DVDD c) Total (a+b) 2) INIT_RESET ="L" Note: 1) Varies slightly depending on sampling frequency and the content of the DSP program. 2) This is a reference value when using a crystal oscillator. Most of the supply current during the initial reset state is in the oscillator section; the value varies slightly depending on the type of crystal oscillator and external circuit. Note 1) Note 2) Min Typ Max Unit
34 31 65 5 90
mA mA mA mA
Note 1) Note 2)
112 102 214 17
324
mW mW mW mW

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(4) Digital filter characteristics Values described below are design values, cited for reference. 4-1) ADC Section: (Ta=25C; AVDD,DVDD =3.0V~3.6V; fs=48kHz; HPF=off) Parameter Symbol Min Pass band (-0.02dB) PB 0 (-6.0dB) 0 Stop band (Note 1) SB 26.5 Pass band ripple (Note 2) PR Stop band attenuation (Note3,4) SA 80 Group delay distortion GD Group delay (Ts=1/fs) GD
Typ 24.00
Max 21.768
0.005 0 29.3
Unit kHz kHz kHz dB dB us Ts
Note: : HPF response is not included 1. The stop band is from 26.5kHz to 3.0455MHz when fs = 48kHz. 2. The pass band is from DC to 21.5kHz from DC when fs = 48kHz. 3. When fs = 48kHz, the modulator samples the analog input at 3.072MHz. The input signal is not attenuated by the digital filter in multiple bands (n x 3.072MHz 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency. 4-2) DAC section (Ta=25C; AVDD,DVDD =3.0V~3.6V; fs=48kHz) Parameter Symbol Min Digital filter PB 0 Pass band 0.07dB (Note 1) (-6.0dB) Stop band (Note 1) SB 26.2 Pass band ripple PR Stop band attenuation SA 47 Group delay (Note 2) GD Digital filter+SCF Amplitude characteristics 0~20.0kHz
Typ
Max 21.7 0.07
Unit kHz kHz kHz dB dB Ts dB
24.0
15 0.5
Note: 1. Pass band and stop band frequencies are proportional to "fs" (system sampling rate), and are equal to PB = 0.4535fs (@-0.06dB) and SB = 0.546fs, respectively. 2. Calculated delay time in the digital filter from setting the 24-bit data of both channels on the input data register to the output of analog signal.

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(5) Switching characteristics 5-1) System clock (AVDD=DVDD=3.0V~3.6V,Ta=-10~70C,CL=20pF) Parameter Symbol Min Master clock (XTI) a) With crystal oscillator 384fs: frequency fMCLK 12.288 512fs: frequency fMCLK 16.384 b) With external clock: 40 Duty factor (18.432MHz) 45 (>18.432MHz) :Frequency fMCLK 10.0 : High level width tMCLKH 16 : Low level width tMCLKL 16 Clock rise time tCR Clock fall time tCF LRCLK sampling frequency Slave mode :clock rise time Slave mode :clock fall time fs tLR tLF 48 150 150 32
Typ
Max
Unit
18.432 24.576 50 50 24.576
19 25 60 55 25 6 6
MHz MHz % MHz ns ns ns ns kHz fs ns ns fs ns ns ns ns
48 1
50 6 6
fBCLK BITCLK Note 1) Slave mode: High level width tBCLKH Slave mode: Low level width tBCLKL Slave mode :clock rise time tBR Slave mode :clock fall time tBF Note 1) 48fs mode can only be applied in slave mode. 5-2) Reset (AVDD=DVDD=3.0V~3.6V,Ta=-10~70C,CL=20pF) Parameter Symbol tRST INIT_RESET Note 1) S_RESET tRST
64 6 6
min 150 150
typ
max
Unit ns ns
Note 1) "L" is acceptable when power is turned on, but "H" requires a stable master clock input.

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5-3) Audio interface (AVDD=DVDD=3.0V~3.6V,Ta=-10~70C,CL=20pF) Parameter Symbol Slave mode BITCLK frequency fBCLK BITCLK low level width tBCLKL BITCLK high level width tBCLKH Delay time from BITCLK"" to LRCLK tBLRD Delay time from LRCLK to BITCLK "" tLRBD Delay time from LRCLK to serial data tLRD output Delay time from BITCLK to serial data tBSOD output Serial data input latch hold time tBSIDS Serial data input latch setup time tBSIDH Master mode BITCLK frequency fBCLK BITCLK duty factor Delay time from BITCLK"" to LRCLK tBLRD Delay time from LRCLK to BITCLK"" tLRBD Delay time from LRCLK to serial data tLRD output Delay time from BITCLK to serial data tBSOD output Serial data input latch hold time tBSIDS Serial data input latch setup time tBSIDH
Min 48 150 150 40 40
Typ 64
Max
Unit fs ns ns ns ns ns ns ns ns
80 80 40 40 64 50 40 40 80 80 40 40
fs % ns ns ns ns ns ns

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5-4) Microcontroller interface (AVDD=DVDD=3.0V~3.6V,Ta=-10~70C,CL=20pF) Parameter Symbol Microcontroller interface signal tWRF RQ Fall time RQ Rise time SCLK fall time SCLKrise time SCLK low level width SCLK high level width Microcontroller to AK7740 Time from RESET "" to RQ "" Time from RQ "" to RESET "" Note 1) RQ high level width Time from RQ "" to SCLK"" Time from SCLK"" to RQ "" SI latch setup time SI latch hold time AK7740 to microcontroller Time from SCLK"" to DRDY"" Time from SI""to DRDY"" SI high level width Delay time from SCLK"" to SO output AK7740 to microcontroller (RAM DATA read-out) SI latch setup time (SI="H") SI latch setup time (SI="L") SI latch hold time Time from SCLK"" to SO tWRQH tWSC tSCW tSIS tSIH tSDR tSIDR tSIH tSOS 200 200 6xtMCLK 100 100 3xtMCLK 3xtMCLK 3xtMCLK 100 ns ns ns ns ns ns ns ns ns tWRR tSF tSR tSCLKL tSCLKH tREW tWRE
min
typ
max 8 8 8 8
Unit ns ns ns ns ns ns ns ns
30 30 200 200
tRSISH tRSISL tRSIH tSOD
30 30 30 100
ns ns ns ns
Note 1) Except for external jump code set at reset state.

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(6) Timing waveform 6-1) System clock 1/fMCLK 1/fMCLK tMCLK=1/fMCL
XTI
tCR tCF
VIH VIL
tMCLK 1/fs 1/fs
tMCLK
LRCLK
tLR 1/fBCLK 1/fBCLK tLF
VIH VIL
tBCLK=1/fBCLK
BITCLK
tBR tBCLK 6-2) Reset signal INIT_RESET S_RESET tRST VIL tBCLK tBF
VIH VIL

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6-3) Audio interface
LRCLK
tBLRD tLRBD
50%DVDD
BITCLK
tLRD tBSOD
50%DVDD
SDOUT SDOUTA
tBSIDS tBSIDH
50%DVDD
SDIN SDINA
50%DVDD

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6-4) Microcontroller interface * Microcontroller interface signals
RQ
tWR
tWR
VIH VIL
tSF
tSR VIH VIL tSCLKL tSCLKH
SCLK
* Microcontroller to AK7740
tREW
tWRE 50%DVDD
S_RESET
RQ
tWRQ
50%DVDD 50%DVDD tWSC tSCW 50%DVDD
SCLK
tWSC tSCW
SI
tSIS tSIH
NOTE : Timing for RUN state is the same except that RESET is set to a "H" RESET represents system reset in normal use.

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AK7740 to microcontroller (DBUS data) 1) DBUS data for 24-bit data output. S_RESET DVDD 50%DVDD DVSS DVDD 50%DVDD DVSS 50%DVDD DVSS tSDR 50%DVDD
RQ
SI DRDY
tSOS
50%DVDD 50%DVDD
SCLK SO
2) DBUS data for less than 24-bits data output (when using SI)
S_RESET RQ
tSIH
DVDD 50%DVDD DVSS DVDD 50%DVDD DVSS 50%DVDD 50%DVDD
SI DRDY SCLK
tSOS tSIDR
50%DVDD
SO
50%DVDD

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AK7740 to microcontroller (RAM DATA read-out) 50%DVDD DVSS 50%DVDD DVSS tRSISL 50%DVDD tRSIS tRSIH 50%DVDD 50%DVDD
S_RESET RQ SI
SCLK SO
tSOD

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Functional Description
(1) Various setting 1-1) SMODE : slave and master mode selector pin Sets LRCLK and BITCLK to either input or output. a) Slave mode :SMODE="L" b) Master mode: SMODE="H" LRCLK (1fs) and BITCLK (64fs or 48fs ) are inputs. LRCLK (1fs) and BITCLK (64fs) are outputs.
Note) SMODE is required to be fixed "L" or "H". After releasing initial reset ( INIT_RESET ="L""H"), this pin may only change during a system reset state ( S_RESET ="L") . In slave mode, phase matching between internal and external clocks start when system reset is released (see (8.(4)), resetting). Do not change SMODE during normal operation. (2) Control registers The control registers can be set via the microcontroller interface in addition to the control pins.These registers consist of four parts, and each register contains 8-bits. For details about writing to the control registers, see the description of the microcontroller interface.This section describes the control register maps. TEST: for TEST (input 0,X: input data ignored, but a 0 should be written). D6 D5 D4 D3 D2 D1 D0 Default
Command Code Write Read
60h 64h 68h 6Ch 70h 74h 78h 7Ch
Name
D7
CONT0 CONT1 CONT2 CONT3
CKS1 DATARAM SW2 ISEL[2]
CKS0 RM SW1 ISEL[1]
DIF BANK[1] SW0 ISEL[0]
DIF1 BANK[0] PSDA2 SW3
DIF0 CMP_N PSDA1 OUTAE
DISCK SS[1] TEST PSAD
SELCKO SS[0] TEST TEST
X X X X
00h 00h 00h 00h
Data can be loaded into the control registers only when S_RESET = "L". Do not attempt to change any value in the control register when S_RESET = "H". 1. CONT0 can be set only when system reset ( S_RESET = "L"). 2. CONT1~3 should be set when system reset ( S_RESET = "L"), otherwise noise will be output. Prior to changing the input selector (CONT3: ISEL[2:0], clocks should be applied and the ADC should be in normal operation mode. The ADC is powered up by setting CONT3:PSAD = 0. Spontaneous changes to the input selector may result in output noise (generated in the ADC data), so an external mute circuit after the DAC output may be required. 3. Default setting is the same value that is initialized by initial reset ( INIT_RESET ="L" ).

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2-1) CONT0 : clock and interface selector This register is enabled only during system reset state ( S_RESET ="L"). Command Code Write Read
60h 70h
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
CONT0
CKS1
CKS0
DIF
DIF1
DIF0
DISCK
SELCKO
X
00h
D7,D6:CKS1 CKS0 master clock select Mode 1 2 3 4 CKS1(D7) 0 0 1 1 CKS0(D6) 0 1 0 1 512fs 384fs(Program steps of DSP are also limited 384 steps) TEST TEST
D5:DIF audio interface selector 0: MSB-justified 2 2 1: I S compatible (all input / output pins are I S compatible) D4, D3:DIF1, DIF0 SDIN input mode selector Mode D4 D3 1 0 0 MSB justified (24bit) 2 0 1 LSB justified (24bit) 3 1 0 LSB justified (20bit) 4 1 1 LSB justified (16bit) Note) When D5 = 1, the state is I S compatible independent of mode setting, but set this register to Mode 1. D2:DISCK LRCLK,BITCLK output control 0: Normal Operation 2 1: Sets BITCLK = "L" and LRCLK = "H" int master mode. (for I S compatible setting, it changes to LRCLK="L".) This setting is only available for analog input and analog output. When this mode is selected, SDIN and SDOUT are not available. D1:SELCKO CLKO output selector. 0: CLKO outputs the same frequency as XTI. 1: CLKO outputs "L" level. After setting CONT0 (when the last clock of SCLK rises), CLKO frequency will change. D0: Always 0 Note) Underlined settings for ~ indicates default.
2

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2-2) CONT1: RAM control Command Code Write Read
64h 74h
Name
D7
D6
D5
D4
D3
D2
D1
D0 Default
CONT1
DATARAM
RM
BANK[1]
BANK[0]
CMP_N
SS[1]
SS[0]
X
00h
D7: DATARAM addressing mode selector 0:Ring addressing mode 1:Linear addressing mode DATARAM has 256-word x 24-bit with two address pointers (DP0, DP1). Ring addressing mode: increments starting address by one every sample. Linear addressing mode: starting address is always the same: DP0 = 00h and DP1 = 80h. D6:RM: decompress bit mode 0: SIGN bit 1: Random data When the compress and decompress function is selected (D3:CMP_N = 0), this bit determines the content o f the decompressed LSB bits. D5,D4:BANK[1:0] DLRAM setting Mode D5 D4 Memory 0 0 0 24bit 3kword (RAM A) 1 0 1 12bit 6kword (RAM A) 2 1 0 12bit 4kword (RAM A),24bit 1kword (RAM B) 3 1 1 24bit 1kword (RAM A),12bit 4kword (RAM B) Note) In mode 0 or 1, both pointer 0 and 1 are available for both RAM A and B. In mode 2 or 3, pointer 0 is available for RAM A and pointer 1 is available for RAM B. D3:CMP_N 12bitDLRAM compress & decompress selector In mode 1,2 or 3, this register turns the compress / decompress function ON or OFF. 0: Compress & decompress function ON When writing to DLRAM the DBUS data is compressed to 12-bits, and when reading from DLRAM, the data is decompressed to 16-bits. 1: Compress & decompress function OFF 12-bits of DBUS data is always written to DLRAM, and 12-bit data is read from the DLRAM and 000h is added for the LSB bits. D2,D1:SS[1:0] DLRAM setting of sampling timing (only for RAM A) Mode D2 D1 RAM A mode selected by BANK[1:0] 0 0 0 Update every sampling time 1 0 1 Update every 2 sampling time 2 1 0 Update every 4 sampling time 3 1 1 Update every 8 sampling time Note) When the mode 1,2 or 3 is selected, it comes out aliasing. D0: Input always 0 Note) Underlined settings for ~ indicates default.

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2-3) CONT2 : DAC ,DSP control
Command Code Write Read
68h 78h
Name
D7
D6
D5
D4
D3
D2
D1
D0
Defaul t
00h
CONT2
SW2
SW1
SW0
PSDA2
PSDA1
TESTT
TEST
X
D7,D6,D5: SW2, SW1, SW0 internal path setting SW2(D7) 0 SW1(D6) 0 SW0(D5) 0 Normal operation
These settings are reserved for test; set these values to "0" (refer to the block-diagram). D4:PSDA2 DAC2 power down control 0:Normal operation 1:DAC2 power down If not using DAC2, set this value to "1", and DAC2 will RESET. When changing to normal operation, set this value to "0" at system reset. D3:PSDA1 DAC1 power down control 0:Normal operation 1:DAC1 power down In the case of not using DAC1, set this value to "1" and DAC1 will be in RESET. When changing to normal operation, set this value to "0" at system reset. D2:TEST 0:Normal operation 1:Test mode (Do NOT use this mode) D1:TEST 0:Normal operation 1:Test mode (Do NOT use this mode) D0: Always input 0 Note): Underlined settings for ~ indicates default.

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2-4) CONT3: ADC control Command Code Write Read
6Ch 7Ch
Name
D7
D6
D5
D4
D3
D2
D1
D0
Defaul t
00h
CONT3
ISEL[2]
ISEL[1]
ISEL[0]
SW3
OUTAE
PSAD
TEST
X
D7,D6,D5:ISEL[2:0] analog input selector setting ISEL[2](D7) ISEL[1](D6) ISEL[0](D5) 0 0 0 1 0 0 1 0 1 1 1 0 1 1 1 D4: SW3 internal path setting 0:Normal operation (ADC SDATA select) 1:DSP SDOUTD1 select D3:OUTAE SDOUT disable 0:SDOUTA="L" 1:Output data selected by SW3 D2:PSAD ADC power down 0:Normal operation 1:ADC power down
Analog input pin AINL-,AINL+,AINR-,AINR+ AINL1,AINR1 AINL2,AINR2 AINL3,AINR3 AINL4,AINR4
When not using the ADC, set this value to "1", and the ADC will be in RESET. The digital output data of the ADC will 00000h in power down mode. When changing to normal operation, set this value to "0" at system reset. D1:TEST 0:Normal operation 1:TESTmode (Do NOT use this mode ) D0: Always input 0 Note) Underlined settings of ~ indicates default.

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(3) Power supply startup sequence Turn on the power by setting INIT_RESET = "L" and S_RESET = "L". This sets up VREF (analog reference level). Then initizlize the control registers by setting INIT_RESET = "H". Note 1) Only set INIT_RESET during power-up. Note 1): Set INIT_RESET = "H" after starting oscillation when a crystal oscillator is used. This setting time may differ depending on the crystal oscillator and its external circuit. NOTE: Do not stop the system clock (slave mode: XTI, LRCLK, BITCLK, master mode: XTI) except when S_RESET = "L". If these clock signals are not supplied, excess current will flow due to dynamic logic that is used internally, and an operation failure may result. Do not set S_RESET = "H" during INIT_RESET = "L". This will stop the oscillator or cause it to be unstable.
AVDD DVDD INIT_RESET S_RESET
When a crystal oscillator is used, ensure stable oscillation in this period.
Power OF F
Power supply startup sequence

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(4) Resetting The AK7740 has two reset pins: INIT_RESET and S_RESET . The INIT_RESET pin sets up VREF and initializes the AK7740, as shown in "Power supply startup sequence section 3)." The system is reset when S_RESET ="L". (Description of "reset" is for "system reset".) Under of system reset, program write operation executes normally (except for write operation during running). The ADC and DAC sections are also reset during system reset. (The ADC output is MSB first 00000h and the DAC output is AVDD/2). However, VREF will be active and LRCLK and BITCLK in the master mode will be inactive. Release system reset by setting S_RESET to "H", which will activate the internal counter. This counter generates LRCLK and BITCLK in the master mode. When the system reset is released in slave mode, internal timing will be actuated in synchronization with " " of LRCLK (when the standard input format is used). Timing between the external and internal clocks is adjusted at this time. If the phase difference between LRCLK and internal timing is within 1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with the internal timing remaining unchanged. If the phase difference exceeds this range, the phase is adjusted by synchronization with " " of LRCLK (when the standard input format is used). This circuit prevents failure of synchronization with the external circuit. For some time after returning to the normal state after loss of synchronization, normal data will not be valid. Change the frequency of the clock, SMODE or analog input selector while the system is in reset. When S_RESET is set to "H", the reset state is cancelled, and the internal DRAM is cleared from the rising edge of LRCLK. It takes 8fs (167usec at fs = 48kHz) to clear the internal DRAM. The ADC section can output 516 cycles LRCLK after its internal counter starts. (The internal counter starts at the first rising edge of LRCLK in master mode. In slave mode, it starts at the end of 2-LRCLK after release of system reset.) The AK7740 is in normal operation mode when S_RESET is set to "H". When INIT_RESET or S_RESET changes, the status of the DAC section also changes to power down or release mode, which causes a click noise at the output. The SMUTE function does not mute this click, ao an external mute circuit is required to avoid any click noise.

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(5) System clock The required system clock is XTI (384fs/512fs), LRCLK (fs) and BITCLK (64fs) in the slave mode, and it is XTI (384 fs/512 fs) in the master mode. LRCLK corresponds to the standard digital audio rate (32 kHz, 44.1 kHz, and 48 kHz). Fs 32.0kHz 44.1kHz 48.0kHz XTI(Master Clock) 512fs 384fs 16.3840MHz 12.2880MHz 22.5792MHz 16.9344MHz 24.576MHz 18.4320MHz BITCLK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
5-1) Master clock (XTI pin) The master clock is produced by connecting a crystal oscillator between the XTI pin and XTO pin or by inputting an external clock into the XTI pin while the XTO pin is left open. 5-2) Slave mode The required system clock is XTI, LRCLK (1 fs) and BITCLK (48/64fs). The master clock (XTI) and LRCLK must be synchronized, but the phase is not critical. 5-3) Master mode The required system clock is XTI (384fs/512fs). When the master clock (XTI) is input, LRCLK (1fs) and BITCLK (64fs) will be outputted from the internal counter synchronized with the XTI. LRCLK and BITCLK will not be active during initial reset ( INIT_RESET ="L") and system reset ( S_RESET ="L").

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(6) Audio data interface (internal connection mode) The serial audio data pins SDIN, SDINA, SDOUT and SDOUTA are interfaced with an external system, using LRCLK and BITCLK. The control registers (CONT2 and CONT3) set the audio interface parameters. The default 2 data format is MSB-first two's complement. The data format can be changed to I S compatible mode by setting the 2 control register CONT0:DIF (D5) to "1" (all input/output audio data pin interfaces are in I S compatible mode.) The input SDIN and SDINA formats are MSB justified 24-bit at initialization. Setting the control registers CONT0: DIF1 (D4), DIF0 (D3) will cause SDIN to be compatible with LSB justified 24-bit, 20-bit and 16-bit. (SDINA is fixed to 24-bit MSB justified only) (Note: CONT0 DIF(D5)=0). Individual setting of SDIN and SDINA is not allowed. The output SDOUT is fixed at 24-bit MSB justified only. In slave mode, BITCLK corresponds to both 64fs and 48fs. 64fs is the recommended BITCLK. 64fs examples are illustrated here: 6-1) Standard input format (DIF = 0: default set value) a) Mode 1 (DIF1, DIF0 = 0,0: default set value) LRCLK BITCLK
31 30 29 10 9 8 7 6 21L M : MSB, L : LSB 5432 1 0 31 30 29 M 22 21 10 9 8 7 6 21L 5432 10
Left ch
Right ch
SDIN,SDINA
M 22 21
* For MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB. b) Mode 2, Mode 3, Mode 4 LRCLK BITCLK
31 30 23 22 21 20 19 18 17 16 15 M 22 21 20 19 18 17 16 15
Left ch
1 1 0 31 30 L Don't Care
Right ch
23 22 21 20 19 18 17 16 15 M 22 21 20 19 18 17 16 15
1 1
0 L
SDIN mode2 SDIN mode3 SDIN mode4 SDIN SDIN SDIN
Don't Care
Don't Care
M 18 17 16 15
1
L
Don't Care
M 18 17 16 15
1
L
Don't Care
M
1
L
Don't Care
M
1
L
Mode 2: (DIF1, DIF0) = (0, 1) LSB justified 24-bit Mode 3: (DIF1, DIF0) = (1, 0) LSB justified 20-bit Mode 4: (DIF1, DIF0) = (1, 1) LSB justified 16-bit
M : MSB, L : LSB

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6-2) I2S compatible input format (DIF=1) LRCLK BITCLK
31 30 29 28 987 2 1L 6 54 3 2 1 0 31 30 29 28 M 22 21 98765432 2 1L 10
Left ch
Right ch
SDIN,SDINA
M 22 21
M : MSB, L : LSB
Mode 1: (DIF1(D4), DIF0(D3)) = (0, 0) must be set. 6-3) Standard output format (DIF=0: default set value) LRCLK BITCLK
31 30 29 10 9 8 7 2 1L 654 3 2 1 0 31 30 29 M 22 21 10 9 8 7 6 5 4 3 2 1 0 2 1L
Left ch
Right ch
SDOUT SDOUTA
M 22 21
M : MSB, L : LSB
6-4) I2S compatible output format (DIF=1)
LRCLK BITCLK
31 30 29 28
Left ch
Right ch
6 54 3 2 1 0 31 30 29 28 M 22 21 987 2 1L 6 54 3210
987 2 1L
SDOUT SDOUTA
M 22 21
M : MSB, L : LSB

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(7) Interface with microcontroller The microcontroller interface consists of six control signals; RQ (request), SCLK (serial data input clock), SI (serial data input), SO (serial data output), RDY (ready) and DRDY (data ready). Both write and read operations are enabled during system reset and run modes. During reset , writing to the control register, program RAM, coefficient RAM, offset RAM, external conditional jump code, and reading from the program RAM, coefficient RAM and offset RAM, are enabled. During the run phase, writing of coefficient RAM, offset RAM and external conditional jump code, and reading of data on the DBUS (data bus) from the SO, are enabled. The data is MSB first serial I/O. To transfer data to the microcontroller, start by setting RQ "L", which enables a data read from the DBUS. The AK7740 reads SI data when SCLK rises, and outputs to SO when SCLK falls. The data format is command followed by address. When RQ changes to "H", then one command is finished. New command requests require setting RQ to "L" again. When the DBUS data is read, leave RQ ="H" (command code input is not required).
Conditions for use RESET phase
Code name CONT0 CONT1 CONT2 CONT3 PRAM CRAM OFRAM External condition jump Test CRAM rewrite preparation CRAM rewrite OFRAM rewrite preparation OFRAM rewrite External condition jump
RUN phase
Command Code List Command code Note: WRITE READ 60h 70h For the function of each bit, See the description of Control 64h 74h Registers 68h 78h 6Ch 7Ch C0h C1h A0h A1h 90h 91h C4h 82h Reserved for test A8h Must occur before CRAM rewrite A4h 98h 94h C4h Must occur before OFRAM rewite Same command as RESET
NOTE: Do not send any other command codes. If there is no communication with the microcontroller, set the SCLK to "H" and the SI to "L" for use.

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7-1) Write during reset phase
7-1-a) Control register write (during reset phase) The data is comprised of two bytes that perform control register write operations (during reset phase). When the current data has been entered, the new data is sent when the 16th cycle of SCLK. Data transfer procedure Command code 60h,64h,68h,6Ch Control data (D7 D6 D5 D4 D3 D2 D1 D0) For the function of each bit, see the description of control registers, (section 2).
S_RESET
RQ SCLK SI SO Note) It must be set always 0 to D0 Control registers write operation 60h D7 ***D1 D0 64h D7 ***D1 D0

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7-1-b) Program RAM writes (during reset phase) Write to the Program RAM during the reset phase with data consisting of a set of seven bytes. When all data has been transferred, the RDY terminal is set "L". Upon completion of the PRAM write, RDY returns "H" to allow the next data bit input. When writing data of continuous addresses, input the data as they are (no command code or address is required). To write discontinuous data, shift the RQ terminal from "H" to "L" again. Then input the command code, address and data in that order. Data transfer procedure Command code C0h Address upper Address lower Data Data Data Data
S_RESET
( 1 1 0 0 0 0 0 0) ( 0 0 0 0 0 0 0 A8) (A7 . . . . . . . A0) (D31 . . . . . . D24) (D23 . . . . . . D16) (D15 . . . . . . D8) (D7 . . . . . . D0)
RQ SCLK SI RDY SO Input of continuous address data into PRAM
S_RESET
11000000
0000000
A7 ****A1A0
D31***** D0
D31***** D0
RQ SCLK SI RDY SO Input of discontinuous address data into PRAM 11000000 0000000A8 A7**A1A0 D31***D0 11000000 0000000A8 A7**A1A0

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7-1-c) Coefficient RAM write (during reset phase) The data comprising a set of five bytes is used to perform coefficient RAM write operations (during reset phase). When all data has been transferred, the RDY terminal goes "H". Upon completion the CRAM write, RDY goes to "H" to allow the next data to be inputted. When writing data of continuous addresses, input the data as they are (no command code or address is required). To write discontinuous data, shift the RQ terminal from "H" to "L". Then input the command code, address and data in that order. Data transfer procedure Command code A0h Address upper Address lower Data Data
S_RESET
(1 0 1 0 0 0 0 0) ( 0 0 0 0 0 0 0 A8) (A7 . . . . . . . A0) (D15 . . . . . . D8) (D7 . . . . . . D0)
RQ SCLK SI RDY SO Input of continuous address data into CRAM
S_RESET
10100000
0000000 A8
A7****A1A0
D15****D0
D15****D0
RQ SCLK SI RDY SO Input of discontinuous address data into CRAM 10100000 0000000 A8 A7***A1A0 D15****D0 10100000 0000000 A8 A7***A1A0 D15*

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7-1-d) Offset RAM write (during reset phase) The data comprising a set of five bytes is used to perform offset RAM write operations (during reset phase). When all data has been transferred, the RDY terminal goes to "H". Upon completion of writing into the OFRAM, RDY goes to "H" to allow the next data to be input. When data of continuous addresses are written, input the data as they are. To write discontinuous data, shift the RQ terminal from "H" to "L". Then input the command code, address and data in that order. Data transfer procedure Command code 90h Address Data Data Data
S_RESET
(1 0 0 1 0 0 ( 0 0 A5 A4 .. . (0 0 0 0 0 0 (0 0 0 D12 D11 * (D7 . . . . .
0 0) . A0 ) 0 0) * . D8 ) . D0 )
RQ SCLK SI RDY SO Input of data into OFRAM 10010000 00A5****A0 00000000 000D12***D8 D7****D1D0

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7-1-e) External conditional jump code write (during reset phase) The data comprising a set of two bytes is used to perform an external conditional jump code write operation. Input the data during either the reset or operation phase, and the input data are set to the specified register at the leading edge of the LRCLK. When all data bits have been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will be executed if there is any one agreement between "1" of each bit of external condition code eight bits (soft set), plus one bit (hard set) at the external input terminal JX and "1" of each bit of the IFCON field. The data during the reset phase can be written only before release of the reset, after all data has been transferred. RQ Transition from "L" to "H" in the write operation during the reset phase must be executed after three LRCLK in slave mode or one LRCLK in master mode, respectively, from the trailing edge of LRCLK after release of the reset. Then RDY goes to "H" after capturing the rise of the next LRCLK. Write operations from the microcontroller are disabled until RDY goes to "H". The IFCON field provides external conditions written on the program. It resets to 00h by INIT_RESET ="L", however, it remains previous condition even S_RESET ="L". Note: LRCLK phase is inverted in the I S-compatible mode. 7 External condition code Check if there is any one agreement between the bit specified in IFCON and "1" in the external condition code 16 8 IFCON field Data transfer procedure Command code C4h ( 1 1 0 0 0 1 0 0) Code data (D7 . . . . . D0) Max 1LRCLK
S_RESET
2
0 JX
SCLK SI SO RQ LRCLK RDY L ch R ch 11000100 D7 **** D0
2LRCLK(max) Timing for external conditional jump write operation (during reset phase)

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7-2) Read during reset phase 7-2-a) Control register data read (during reset phase) To read data written into the control registers, input the command code and 16 bits of SCLK. After the command code input, the data D7 to D1 outputs from SO synchronized with the falling edge of SCLK. D0 is invalid, so ignore this bit. Data transfer procedure Command code 70h,74h,78h,7Ch
S_RESET
RQ SCLK SI SO 70h (example) D7 **** D1 74h (example) D7 **** D1
Reading of Control Register data

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7-2-b) Program RAM read (during reset phase) To read data written into PRAM, input the command code and the address to be read out. After that, set SI to "H" and SCLK to "L". The data is clocked out from SO synchronized with the falling edge of SCLK (ignore the RDY operation that will occur in this case). If there are continuous addresses to be read, repeat the above procedure starting from the step where SI is set to "H". Data transfer procedure Command code input C1h ( 1 1 0 0 0 0 0 1 ) Read address input MSB ( 0 0 0 0 0 0 0 A8) Read address input LSB (A7 . . . . A0)
S_RESET
RQ SCLK SI SO RDY Reading of PRAM data 11000001 0000000 A8 A7 **** A1 A0 D31 **** D0 D31 **** D0

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7-2-c) CRAM data read (during reset phase) To read out the coefficient data, input the command code and the address to be read out. After that, set SI to "H" and SCLK to "L". The data is clocked out from SO synchronized with the falling edge of SCLK.If there are continuous addresses to be read, repeat the above procedure starting from the step where SI is set to "H". Data transfer procedure Command code A1h Address upper Address lower
S_RESET
(1 0 1 0 0 0 0 1) ( 0 . . . . . . A8) (A7 . . . . . . A0)
RQ SCLK SI SO RDY Reading of CRAM data 10100001 0000000A8 A7 **** A1A0 D15 **** D0 D15 **** D0

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7-2-d) OFRAM data read (during reset phase) Read out the offset data during the reset phase. To read it, input the command code and the address to be read. After that, set SI to "H" and SCLK to "L". This completes preparation for outputting the data. Set SI to "L", and the data is clocked out synchronized with the falling edge of SCLK. If there are continuous addresses to be read, repeat the above procedure starting from the step where SI is set to "H". Data transfer procedure Command code Address 91h ( 1 0 0 0 1 0 0 0 1 ) ( 0 0 A5 . . . . A0)
S_RESET
RQ SCLK SI SO RDY 10010000 00 A5 **** A0 D12 *** D1 D0 D12 *** D1 D0 D12 *** D1 D0
Reading of OFRAM data

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7-3) Write during RUN phase 7-3-a) CRAM rewrite preparation and write (during RUN phase) This function is used to rewrite CRAM (coefficient RAM) during program execution. After inputting the command code, input a maximum of 16 data bytes to rewrite to a continuous address. Then input the write command code and rewrite the leading address. Every time the RAM address to be rewritten is specified, the contents of RAM are rewritten. The following is an example to show how five data bytes from address "10" of the coefficient RAM are rewritten: Coefficient RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15 Rewrite position Note that address "13" is not executed until address "12" is rewritten. Data transfer procedure * Preparation for rewrite Command code A8h ( 1 0 1 0 1 0 0 0 ) Data ( D15 . . . . D8 ) Data ( D7 . . . . . D0 ) * Rewrite Command code A4h ( 1 0 1 0 0 1 0 0 ) Address upper ( 0 0 0 0 0 0 0 A8 ) Address lower (A7 . . . . A0 )
S_RESET
RQ SCLK SI 10101000 D15 **** D0 10100100 A15 **** A0 AL RDY Longer of (16-n) x 2 MCLK (n: number of data) and AL SO Note: The RDY signal will go to high within the maximum of two LRCLKs if the RDYLG width is programmed to ensure a new address to be rewritten within one sampling cycle. RDYLG max 200ns
CRAM rewriting preparation and writing

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7-3-b) OFRAM rewrite preparation and write (during RUN phase) This function is used to rewrite OFRAM (offset RAM) during program execution. After inputting the command code, input a maximum of 16 data bytes to rewrite to a continuous address. Then input the write command code and rewrite the leading address. Every time the RAM address to be rewritten is specified, the contents of RAM are rewritten. The following is an example to show how five data bytes from address "10" of the coefficient RAM are rewritten: Offset RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15 Rewrite position Note that address "13" is not executed until address "12" is rewritten. Data transfer procedure * Preparation for rewrite Command code 98h ( 1 0 0 0 1 1 0 0 0 ) Data (D23 . . . . . . D16) Data (D15 . . . . . . D8 ) Data ( D7 . . . . . . D0 ) * Rewrite Command code 94h ( 1 0 0 0 1 0 1 0 0 ) Address ( 0 0 A5A4 . . . A0)
S_RESET
RQ SCLK SI 10011000 D23 **** D0 10010100 00 A5***A0 AL RDY
(Longer of (16-n) x 2 MCLK (n: number of data) and AL
max 200ns
RDYLG
SO Note: The RDY signal will go to high within the maximum of two LRCLKs if the RDYLG width is programmed to ensure a new address to be rewritten within one sampling cycle.
OFRAM rewriting preparation and writing

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7-3-c) External conditional jump code rewrite (during RUN phase) Data comprising a set of two bytes is used to write the external conditional jump code. Data can be input during both the reset and operation phases, and input data is set to the specified register at the rising edge of LRCLK. When all data has been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will be executed if there is any one agreement between each bit of the 8-bit external condition code and "1"of each bit of the IFCON field. A write operation from the microcontroller is disabled until RDY goes to "H". Note: The LRCLK phase is inverted in the I2S-compatible mode.
Data transfer procedure Command code C4h ( 1 1 0 0 0 1 0 0 ) Code data (D7 . . . . . D0) max 1LRCLK
S_RESET
SCLK SI SO RQ LRCLK RDY max 2LRCLK L ch R ch 11000100 D7 *** D0
max0.25LRCLK
External condition jump write timing (during RUN phase)

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7-4) Read-out during RUN phase (SO output ) SO outputs data on DBUS (data bus) from the DSP section. Data is set when the @MICR command is executed in the DSP program. Setting the data allows DRDY to go to "H", and data is output synchronized with the falling edge of SCLK. When SI goes "H", DRDY goes to "L" to wait for the next command. Once DRDY goes "H", the data from the last @MICR command immediately before DRDY went "H" is held until SI goes "H", and subsequent commands will be rejected. A maximum of 24 bits are output from SO. After the required number of data (not exceeding 24 bits) is taken out by SCLK, setting SI to "H" can output the next data.
S_RESET
RQ SI @MICR DRDY SCLK SO
DM Data1 DLSB DM Data2 DLSB
Data1
Data2
SO read (during RUN phase) The SI pin controls clearing the output buffer (MICR). When reading this data, be aware that state changes on SI are asynchronous to the audio sampling clock, which may result in noise in the audio sugnal.

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(8) ADC section high-pass filter The AK7740 incorporates a digital high-pass filter (HPF) for cancelling DC offset in the ADC section. The HPF cut-off frequency is 1 Hz (fs = 48 kHz). This cut-off frequency is proportional to the sampling frequency (fs). Cut-off frequency 48kHz 0.93Hz 44.1kHz 0.86Hz 32kHz 0.62Hz

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9. System Design
9-1) Connection example
0.1u 0.1u 0.1u
Digital +3.3V
10u
10 15 18 19 16 17
Rd Cd
24
32
DVDD SMODE SDIN SDINA LRCLK BITCLK XTO XTI CLKO DRDY SO RDY 22 26 25 29 27 28 14
Micom I/F
RQ
SI SCLK
12
Cd
11 13 RESET
AK7740
JX
31 INIT RESET 30 S RESET 21 SDOUT 20 SDOUTA AINL+ AINLAINR+ AINRAINL1 AINR1 AINL2 AINR2 AINL3 AINR3 AINL4 AINR4 AVSS AVDD VREFH BVSS 34
AOUTL2 36 AOUTR1 37 AOUTL1 38
CONTROL
AVSS AVDD
41 Analog +3.3V 39
0.1u 10u
Analog Lch+ Analog LchAnalog Rch+ Analog RchAnalog 1L Analog 1R Analog 2L Analog 2R Analog 3L Analog 3R Analog 4L Analog 4R
45 44
43 42 5 4 3 2 1 48 47 46 8 7 6
VCOM
40
0.1u 10u
Analog +3.3V
10u 0.1u
AOUTR2
35
10u
0.1u
9,23,33
DVSS

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2006/10
[ASAHI KASEI]
[AK7740ET]
9-2) Peripheral circuit 9-2-3) Ground and power supply
To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7740. System analog power is supplied to AVDD. Generally, power supply and ground wires must be connected separately according to the analog and digital systems. Connect them at a position close to the power source on the PC board. Decoupling capacitors, and ceramic capacitors of small values in particular, should be connected at positions as close as possible to the AK7740.
9-2-4) Reference voltage
The input voltage difference between the VREFH pin and the AVSS pin determines the full scale of analog input, while the potential difference between the VREFH pin and the AVSS pin determines the full scale of the analog output. Normally, connect AVDD to VREFH, and connect 0.1F ceramic capacitors from them to AVSS. To shut out high frequency noise, connect a 0.1F ceramic capacitor in parallel with an appropriate 10F electrolytic capacitor between this pin and AVSS. The ceramic capacitor in particular should be connected at a position as close as possible to the pin. To avoid coupling to the AK7740, digital signals and clock signals in particular should be kept as far away as possible from the VREFH pin. VCOM is used as the common voltage of the analog signal.To filter out high frequency noise, connect a 0.1F ceramic capacitor in parallel with an appropriate 10F electrolytic capacitor between this pin and AVSS. The ceramic capacitor in particular should be connected at a position as close as possible to the pin. Do not lead current from the VCOM pin.
9-2-5) Analog input
Analog input signals are applied to the modulator through the differential or single-ended input pins of each channel selected by the input selector. When using differential inputs, the voltage is equal to the differential voltage between AIN+ and AIN- (VAIN=(AIN+)-(AIN-)), and the input range is FS = (VREFH-AVSS)x(2.0/3.3). When VREFH = 3.3V and AVSS = 0V, the input range is within 2.0Vpp. When using single-ended inputs, the input range is FS = (VREFH-AVSS) x (2.0/3.3). When VREFH = 3.3V and AVSS = 0V, the input range is within 2.0Vpp. The output code format is given in terms of 2's complements. When fs = 48 kHz, the AK7740 samples the analog input at 3.072 MHz. The digital filter eliminates noise from 30 kHz to 3.042 MHz. However, noise is not rejected in the bandwidth close to 3.072 MHz. Most audio signals do not have large noise near 3.072 MHz, so a simple RC filter is sufficient. A/D converter reference voltage is applied to the VREFH and AVSS pins. The analog source voltage to the AK7740 is +3.3V (typical). Voltage of AVDD+0.3V or more, voltage of AVSS-0.3 V or less, and current of 10mA or more must not be applied to the analog input pins (AINL+, AINL-, AINR+, AINR-, AINL1, AINR1, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4 and VREFH). Excessive current will damage the internal protection circuit and will cause latch-up, damaging the IC. Accordingly, if the surrounding analog circuit voltage is 15V, the analog input pins must be protected from signals with the absolute maximum rating or more.

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2006/10
[ASAHI KASEI]
[AK7740ET]
10k +10V 10k 10k 10k 2.00Vpp
Signal
+
-10V
+ NJM5532D
+ 4.7u +
AIN+
AINVop = VA+ = 3.3V
4.7u 2.00Vpp
Fig. 1 Example of input buffer circuit (differential input)
10k +10V 10k 10k 10k 2.00Vpp
Signal
+
-10V
+ NJM5532D
+ 4.7u
AIN
Vop = VA+ = 3.3V
Fig. 2 Example of input buffer circuit (single ended input) An analog signal can be applied to the AK7740 in single ended mode. In this case, apply the analog signal (the full scale is 2.0Vpp when the internal reference voltage is used). However, use of a low saturation operational amplifier is recommended if the operational amplifier is driven by the 3.3-volt power supply. 9-2-6) Analog output Analog output is single-ended, and the output range is 2.00Vpp (typical) with respect to VCOM voltage. The out-of-band noise (from the noise shaper) produced by the internal modulator is reduced by the internal switched capacitor filter (SCF) and continuous time filter (CTF). It is not necessary to add an external filter for normal applications. The input code format is given in terms of two's complement with the positive full-scale output for the 7FFFFFH (@24bit) input code, and the negative full-scale output for the 800000H (@24bit) input code. VCOM voltage is output as an ideal value for 000000H (@24bit) input code.
9-2-7) Connection to digital circuit
To minimize noise resulting from the digital circuit, connect low voltage logic to the digital output. The applicable logic family includes the 74LV, 74LV-A, 74ALVC and 74AVC series.

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2006/10
[ASAHI KASEI]
[AK7740ET]
10. Package
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 37 25 24 9.0 0.2
1.7Max 0.13 0.13 1.4TYP
48 1 0.22 0.08 12
13
7.0
0.16 0.07 0.5 0.10 M
0 10
0.10
0.5 0.2
Material & Lead finish
Package: Lead-frame: Lead-finish Epoxy Copper Soldering plate

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2006/10
[ASAHI KASEI]
[AK7740ET]
11. Marking
AKM
AK7740ET XXXXXXX
1
1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK7740ET 4) Asahi Kasei Logo
IMPORTANT NOTICE
These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.(AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a): A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b): A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.

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2006/10

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